lumiera_/tests/components
Ichthyostega f5290a99a3 OutputSlot : simulated usage protocol passes unit test
OutputSlotProtocol_test

Some parts are still missing
 - timings
 _ initialisation
2012-01-08 03:06:32 +01:00
..
backend spelling and typos 2011-12-24 05:48:31 +01:00
proc OutputSlot : simulated usage protocol passes unit test 2012-01-08 03:06:32 +01:00
DIR_INFO update some DIR_INFO entries 2011-04-05 00:44:30 +02:00
mainsuite.cpp finish common->lib transition for the tests 2008-12-18 04:47:41 +01:00
Makefile.am Fix autotool build again, still fails on setup.ini 2011-09-15 04:35:08 +02:00